For a T-gate or H-gate SOI device, with ultra-thin, or thin, gate oxide, the gate leakage current and parasitic capacitance in additional gate regions will increase Ioff-state leakage and degrade AC performance, respectively. AC performance is active circuit performance. Degraded AC performance is slower circuit speed of active circuits, for example, an inverter, a NAND gate or a NOR gate. The additional gate area increases Ioff and active power dissipation. Further, the low substrate dopant concentration under the additional gate region results in low efficiency of body contact for conventional T-gate and H-gate SOI devices.
A body contact structure is proposed according to B. W. Min et al., “Reduction Of Hysteretic Propagation Delay With Less Performance Degradation By Novel Body Contact in PD SOI Application, 2002 IEEE International SOI Conference, P. 169.
Min proposes a novel body contact structure by growing thicker gate oxide in additional gate regions so that the additional gate capacitance can be reduced. Min proposes a gate oxide of multiple thickness. The gate oxide is thinner under the gate where the gate crosses a channel region of the transistor between the source and drain regions of the transistor. The gate oxide is thicker under the gate polysilicon where the gate polysilicon extends in an additional gate region, so that additional gate capacitance, or gate loading capacitance, can be reduced. However, making the multiple thickness will require a complex set of design rules, and complex manufacturing controls.